#hardware
54 articles
01
·Supply Chain·FREE·8 min read
Mapping the Semiconductor Supply Chain — From Sand to Chip, Who Holds What
One pass through the whole chain that makes a chip — design (EDA/IP), equipment, materials, foundry, OSAT — and why nearly every stage collapses to a handful of firms, read through two formulas: chain availability and HHI.
02
·Supply Chain·FREE·8 min read
Mapping the Semiconductor Supply Chain — From Sand to Chip, Who Holds What
One pass through the whole chain that makes a chip — design (EDA/IP), equipment, materials, foundry, OSAT — and why nearly every stage collapses to a handful of firms, read through two formulas: chain availability and HHI.
03
·Supply Chain·★ MEMBER·13 min read
Upstream of Semiconductors — Wafers, Photoresist, and Specialty Gases
How sand becomes silicon that is 99.999999999% pure, gets pulled out of a melt as one giant single crystal, and is coated with a film that dissolves where light hits it. From segregation in the Czochralski process to acid blur in chemically amplified resist — and why a handful of Japanese firms still own this layer.
04
·Supply Chain·★ MEMBER·13 min read
Upstream of Semiconductors — Wafers, Photoresist, and Specialty Gases
How sand becomes silicon that is 99.999999999% pure, gets pulled out of a melt as one giant single crystal, and is coated with a film that dissolves where light hits it. From segregation in the Czochralski process to acid blur in chemically amplified resist — and why a handful of Japanese firms still own this layer.
05
·Supply Chain·★ MEMBER·9 min read
Inside the Equipment Makers — What ASML, AMAT, TEL and Lam Actually Build
Chip manufacturing is four actions repeated hundreds of times — deposit, print, etch, clean — and each action has its own machine and its own specialist vendor. After mapping steps to suppliers, two pieces of arithmetic explain why the tool business collapses into a handful of firms, and why ASML's EUV monopoly is really a bundle of irreplaceable component makers.
06
·Supply Chain·★ MEMBER·9 min read
Inside the Equipment Makers — What ASML, AMAT, TEL and Lam Actually Build
Chip manufacturing is four actions repeated hundreds of times — deposit, print, etch, clean — and each action has its own machine and its own specialist vendor. After mapping steps to suppliers, two pieces of arithmetic explain why the tool business collapses into a handful of firms, and why ASML's EUV monopoly is really a bundle of irreplaceable component makers.
07
·Supply Chain·★ MEMBER·11 min read
IP Cores and the Fabless Model — How Arm Rules Silicon Without Making a Single Chip
Why a company that only sells blueprints ends up at the center of the chip industry. License fees versus royalties, the shipment volume where buying beats building, the three grades of IP (soft, hard, architectural), and what RISC-V actually made free — and what it did not.
08
·Supply Chain·★ MEMBER·11 min read
IP Cores and the Fabless Model — How Arm Rules Silicon Without Making a Single Chip
Why a company that only sells blueprints ends up at the center of the chip industry. License fees versus royalties, the shipment volume where buying beats building, the three grades of IP (soft, hard, architectural), and what RISC-V actually made free — and what it did not.
09
·Supply Chain·★ MEMBER·10 min read
EDA Tools from Scratch — Chips Are Written in Software
Nobody hand-places the tens of billions of transistors on a leading-edge chip. Designers write text (RTL), and software compiles it into physical geometry through synthesis, place-and-route, and verification. Here is that pipeline from zero, plus why Synopsys and Cadence became impossible to route around.
10
·Supply Chain·★ MEMBER·10 min read
EDA Tools from Scratch — Chips Are Written in Software
Nobody hand-places the tens of billions of transistors on a leading-edge chip. Designers write text (RTL), and software compiles it into physical geometry through synthesis, place-and-route, and verification. Here is that pipeline from zero, plus why Synopsys and Cadence became impossible to route around.
11
·Supply Chain·★ MEMBER·9 min read
The Geopolitics of Chips — Export Controls and Supply Chain Rewiring, Explained Technically
Why chokepoints form exactly where they do, from three conditions: physics, fixed cost, and tacit knowledge. Covers the technical reason controls are written as numeric thresholds, the common-cause formula that kills dual sourcing, and the learning curve that sets how fast a substitute can arrive.
12
·Supply Chain·★ MEMBER·9 min read
The Geopolitics of Chips — Export Controls and Supply Chain Rewiring, Explained Technically
Why chokepoints form exactly where they do, from three conditions: physics, fixed cost, and tacit knowledge. Covers the technical reason controls are written as numeric thresholds, the common-cause formula that kills dual sourcing, and the learning curve that sets how fast a substitute can arrive.
13
·Device Physics·★ MEMBER·12 min read
The Physics of NAND Flash — Remembering by Trapping Electrons
Why does a memory stick keep your photos with the power off? Starting from one idea — trap electrons on an island of insulator and shift a threshold voltage — this article builds up tunnelling writes, multi-level cells, 3D stacking and wear-out, and ends where you can read an SSD datasheet and a SMART log for yourself.
14
·Device Physics·★ MEMBER·12 min read
The Physics of NAND Flash — Remembering by Trapping Electrons
Why does a memory stick keep your photos with the power off? Starting from one idea — trap electrons on an island of insulator and shift a threshold voltage — this article builds up tunnelling writes, multi-level cells, 3D stacking and wear-out, and ends where you can read an SSD datasheet and a SMART log for yourself.
15
·Computer Architecture·★ MEMBER·9 min read
Interconnects — How NVLink, PCIe, and Light Set the Limits of Scale
When adding GPUs stops making things faster, the wiring is usually to blame. This piece pins down the bandwidth hierarchy from HBM through NVLink, PCIe, and the inter-node fabric, breaks collective time into 'steps × latency + bytes ÷ bandwidth', and explains why all-to-all hurts and why distance eventually demands light.
16
·Computer Architecture·★ MEMBER·9 min read
Interconnects — How NVLink, PCIe, and Light Set the Limits of Scale
When adding GPUs stops making things faster, the wiring is usually to blame. This piece pins down the bandwidth hierarchy from HBM through NVLink, PCIe, and the inter-node fabric, breaks collective time into 'steps × latency + bytes ÷ bandwidth', and explains why all-to-all hurts and why distance eventually demands light.
17
·Cloud & Ops·★ MEMBER·10 min read
The Economics of GPU Cloud — Rent, Buy, or Commit
The same GPU carries four prices at once. Put on-demand, committed, spot, and owned hardware on a single equation: the break-even utilization, the true cost of spot once interruptions are priced in, the commitment burn rate, and the line items that never appear on the rate card.
18
·Fabrication & Packaging·★ MEMBER·11 min read
Yield and Design — DFM, the Art of Giving Something Up
A circuit can be correct in simulation and still fail to make money in volume. Defect density models and the clustering factor, design rules that restrict what shapes you may draw, redundancy that assumes breakage, and binning that turns one die into several products — the engineering of trading performance for yield, from first principles.
19
·Fabrication & Packaging·★ MEMBER·11 min read
Yield and Design — DFM, the Art of Giving Something Up
A circuit can be correct in simulation and still fail to make money in volume. Defect density models and the clustering factor, design rules that restrict what shapes you may draw, redundancy that assumes breakage, and binning that turns one die into several products — the engineering of trading performance for yield, from first principles.
20
·Scaling & Power·★ MEMBER·11 min read
Thermal Design from Scratch — The Wall in 3D Stacking Is Heat
Nearly all the power that enters a chip leaves it as heat. Temperature is set by a series stack of thermal resistances, and once you stack dies vertically the hottest layer heats up with the square of the layer count. Heat flux and hotspots, the lag that thermal mass introduces, and which term liquid cooling actually removes — picking up where the power budget left off.
21
·Scaling & Power·★ MEMBER·11 min read
Thermal Design from Scratch — The Wall in 3D Stacking Is Heat
Nearly all the power that enters a chip leaves it as heat. Temperature is set by a series stack of thermal resistances, and once you stack dies vertically the hottest layer heats up with the square of the layer count. Heat flux and hotspots, the lag that thermal mass introduces, and which term liquid cooling actually removes — picking up where the power budget left off.
22
·Computer Architecture·★ MEMBER·PAPER·10 min read
Systolic Arrays — Building the Heart of the TPU From Scratch
Piling on multipliers doesn't make a chip faster, because moving data costs more than the arithmetic does. This piece takes the grid at the center of the TPU — the systolic array — and shows exactly how it maps the triple loop of matrix multiplication onto rows, columns and clock ticks, from a 2×2 hand trace to a cycle-accurate simulator to the batch-size and shape rules you'll actually tune.
23
·Computer Architecture·★ MEMBER·PAPER·10 min read
Systolic Arrays — Building the Heart of the TPU From Scratch
Piling on multipliers doesn't make a chip faster, because moving data costs more than the arithmetic does. This piece takes the grid at the center of the TPU — the systolic array — and shows exactly how it maps the triple loop of matrix multiplication onto rows, columns and clock ticks, from a 2×2 hand trace to a cycle-accurate simulator to the batch-size and shape rules you'll actually tune.
24
·Accelerators·★ MEMBER·9 min read
The Inference Chip Wars — Inside the Design Philosophies of Groq, Cerebras, and the LPU
Inference-only chips exist because decoding is limited by reading, not by arithmetic. From zero background: the two answers — put everything in SRAM (Groq/LPU) and make the chip a whole wafer (Cerebras) — the software counterattack, and the arithmetic you need to read the market without swallowing vendor benchmarks whole.
25
·Accelerators·★ MEMBER·9 min read
The Inference Chip Wars — Inside the Design Philosophies of Groq, Cerebras, and the LPU
Inference-only chips exist because decoding is limited by reading, not by arithmetic. From zero background: the two answers — put everything in SRAM (Groq/LPU) and make the chip a whole wafer (Cerebras) — the software counterattack, and the arithmetic you need to read the market without swallowing vendor benchmarks whole.
26
·Device Physics·★ MEMBER·9 min read
From FinFET to GAA — Why the Transistor Had to Go Vertical
Why did a flat transistor grow a fin, and then become a stack of thin slabs? With three tools — short-channel effects, DIBL, and the natural length — this piece shows that FinFET and GAA nanosheets were not a matter of taste but a corner physics painted the industry into. No prior knowledge assumed.
27
·Device Physics·★ MEMBER·9 min read
From FinFET to GAA — Why the Transistor Had to Go Vertical
Why did a flat transistor grow a fin, and then become a stack of thin slabs? With three tools — short-channel effects, DIBL, and the natural length — this piece shows that FinFET and GAA nanosheets were not a matter of taste but a corner physics painted the industry into. No prior knowledge assumed.
28
·Computer Architecture·★ MEMBER·PAPER·10 min read
CPU Pipelines and Branch Prediction — The Factory Inside One Clock Tick
An instruction appears to finish in a single clock tick because the machine is an assembly line. From the five classic stages, through the three kinds of hazard, to branch prediction, speculative execution, and the day the leftovers of speculation turned into an information leak — Spectre.
29
·Computer Architecture·★ MEMBER·PAPER·10 min read
CPU Pipelines and Branch Prediction — The Factory Inside One Clock Tick
An instruction appears to finish in a single clock tick because the machine is an assembly line. From the five classic stages, through the three kinds of hazard, to branch prediction, speculative execution, and the day the leftovers of speculation turned into an information leak — Spectre.
30
·Scaling & Power·★ MEMBER·10 min read
The Economics of Chiplets — We Split Dies Because We Cannot Build Them Big
Chips are split into chiplets not because splitting is faster but because a single large die cannot be built at a price anyone will pay. The reticle limit, the exponential in yield, cost per good die, the point where splitting starts to lose money, mixing process nodes, and UCIe as a standard for the seam.
31
·Scaling & Power·★ MEMBER·10 min read
The Economics of Chiplets — We Split Dies Because We Cannot Build Them Big
Chips are split into chiplets not because splitting is faster but because a single large die cannot be built at a price anyone will pay. The reticle limit, the exponential in yield, cost per good die, the point where splitting starts to lose money, mixing process nodes, and UCIe as a standard for the seam.
32
·Device Physics·FREE·11 min read
Band Theory from the Ground Up — Why It Had to Be Silicon
What actually separates a conductor from an insulator? Starting from why atomic energy levels smear into bands, this piece builds up bandgaps, Fermi statistics and doping with no prior physics assumed — and lands on the real answer to 'why is every chip made of silicon', which turns out to be about the oxide, not the element.
33
·Device Physics·FREE·11 min read
Band Theory from the Ground Up — Why It Had to Be Silicon
What actually separates a conductor from an insulator? Starting from why atomic energy levels smear into bands, this piece builds up bandgaps, Fermi statistics and doping with no prior physics assumed — and lands on the real answer to 'why is every chip made of silicon', which turns out to be about the oxide, not the element.
34
·Scaling & Power·FREE·10 min read
What Moore's Law Actually Says — What Ended, and What Is Still Going
"Double every two years" was never a law of physics — it was a timetable the industry agreed to keep. Dennard scaling is what ended; cost is what slowed; density and going vertical are what continue. A ground-up tour through log axes, the flat-to-FinFET-to-GAA story, and the arithmetic of cost per transistor.
35
·Scaling & Power·FREE·10 min read
What Moore's Law Actually Says — What Ended, and What Is Still Going
"Double every two years" was never a law of physics — it was a timetable the industry agreed to keep. Dennard scaling is what ended; cost is what slowed; density and going vertical are what continue. A ground-up tour through log axes, the flat-to-FinFET-to-GAA story, and the arithmetic of cost per transistor.
36
·Computer Architecture·★ MEMBER·PAPER·9 min read
The GPU Memory Hierarchy — HBM, SRAM, Registers, and Why Movement Wins
What sets a GPU's speed is not the arithmetic units but where the data sits — registers, shared memory, L2 or HBM — and how many times it is moved. Capacities and bandwidths by order of magnitude, arithmetic intensity and tiling, a roofline per level of the hierarchy, and finally FlashAttention: more FLOPs, less time.
37
·Computer Architecture·★ MEMBER·PAPER·9 min read
The GPU Memory Hierarchy — HBM, SRAM, Registers, and Why Movement Wins
What sets a GPU's speed is not the arithmetic units but where the data sits — registers, shared memory, L2 or HBM — and how many times it is moved. Capacities and bandwidths by order of magnitude, arithmetic intensity and tiling, a roofline per level of the hierarchy, and finally FlashAttention: more FLOPs, less time.
38
·Fabrication & Packaging·★ MEMBER·10 min read
EUV Lithography — The Madness of Making 13.5nm Light
Light at 13.5nm is absorbed by air and by every lens material there is. So why did the semiconductor industry build an entire industry around it? Tin plasma sources, optics with no lenses at all, and the cost arithmetic against multi-patterning — explained from zero.
39
·Fabrication & Packaging·★ MEMBER·10 min read
EUV Lithography — The Madness of Making 13.5nm Light
Light at 13.5nm is absorbed by air and by every lens material there is. So why did the semiconductor industry build an entire industry around it? Tin plasma sources, optics with no lenses at all, and the cost arithmetic against multi-patterning — explained from zero.
40
·Device Physics·★ MEMBER·10 min read
Reading Chip Design as a Power Budget — The Physics of Leakage and Heat
A modern chip is limited not by what fits, but by how much of it can be lit at once. This piece reads that limit as a household budget: dynamic power versus leakage, the positive feedback that makes leakage swell with temperature, the thermal resistance that converts watts into degrees, and the three — and only three — ways a designer can spend the watts.
41
·Device Physics·★ MEMBER·10 min read
Reading Chip Design as a Power Budget — The Physics of Leakage and Heat
A modern chip is limited not by what fits, but by how much of it can be lit at once. This piece reads that limit as a household budget: dynamic power versus leakage, the positive feedback that makes leakage swell with temperature, the thermal resistance that converts watts into degrees, and the three — and only three — ways a designer can spend the watts.
42
·Fabrication & Packaging·★ MEMBER·10 min read
Advanced Packaging — How CoWoS and HBM Stacking Became the Bottleneck for AI
What limited the supply of AI accelerators was not leading-edge logic wafers but the step that puts several finished chips into one part. From the reticle limit and the exponential math of yield, through 2.5D interposers, HBM stacks and TSVs, to hybrid bonding and the bill that heat and warpage send back.
43
·Fabrication & Packaging·★ MEMBER·10 min read
Advanced Packaging — How CoWoS and HBM Stacking Became the Bottleneck for AI
What limited the supply of AI accelerators was not leading-edge logic wafers but the step that puts several finished chips into one part. From the reticle limit and the exponential math of yield, through 2.5D interposers, HBM stacks and TSVs, to hybrid bonding and the bill that heat and warpage send back.
44
·Fabrication & Packaging·★ MEMBER·9 min read
How Chips Are Made — From Wafer to Yield
Every GPU and phone processor starts as sand and passes through hundreds of printing steps. From the basic moves — lithography, etching, ion implantation — to the brute force of EUV and the yield math that makes big dies exponentially expensive, explained from zero.
45
·Fabrication & Packaging·★ MEMBER·9 min read
How Chips Are Made — From Wafer to Yield
Every GPU and phone processor starts as sand and passes through hundreds of printing steps. From the basic moves — lithography, etching, ion implantation — to the brute force of EUV and the yield math that makes big dies exponentially expensive, explained from zero.
46
·Accelerators·★ MEMBER·PAPER·8 min read
How AI Accelerators Are Designed — What Actually Separates GPUs, NPUs, and TPUs
GPUs, TPUs, and NPUs are three different answers to one question: how much generality do you trade away for matrix multiplication? A from-scratch tour of systolic arrays, dataflow design, and the co-evolution of hardware and quantization.
47
·Accelerators·★ MEMBER·PAPER·8 min read
How AI Accelerators Are Designed — What Actually Separates GPUs, NPUs, and TPUs
GPUs, TPUs, and NPUs are three different answers to one question: how much generality do you trade away for matrix multiplication? A from-scratch tour of systolic arrays, dataflow design, and the co-evolution of hardware and quantization.
48
·Device Physics·FREE·9 min read
MOSFETs from the Ground Up — A Sluice Gate Opened by Voltage, and the Reality of Leakage
The switch that fills every CPU and GPU, assuming no prior knowledge. From the sluice-gate analogy to threshold voltage, then the subthreshold leakage equation and why shrinking a transistor makes it leak more — the root of the power problem in one article.
49
·Device Physics·FREE·9 min read
MOSFETs from the Ground Up — A Sluice Gate Opened by Voltage, and the Reality of Leakage
The switch that fills every CPU and GPU, assuming no prior knowledge. From the sluice-gate analogy to threshold voltage, then the subthreshold leakage equation and why shrinking a transistor makes it leak more — the root of the power problem in one article.
50
·Scaling & Power·★ MEMBER·9 min read
The Physics of Power — Why Lowering Voltage Pays So Much
Derive what one switching event costs, then read the dynamic power equation to see why voltage alone enters squared. From there: Dennard scaling and its end, the 60 mV/decade thermodynamic floor, dark silicon, and the resulting turn toward fixed-function circuits and low precision — ending with the arithmetic of what inference costs to run.
51
·Scaling & Power·★ MEMBER·9 min read
The Physics of Power — Why Lowering Voltage Pays So Much
Derive what one switching event costs, then read the dynamic power equation to see why voltage alone enters squared. From there: Dennard scaling and its end, the 60 mV/decade thermodynamic floor, dark silicon, and the resulting turn toward fixed-function circuits and low precision — ending with the arithmetic of what inference costs to run.
52
·Accelerators·FREE·9 min read
How Numbers Are Represented — From FP32 to FP8 and INT4
Open up the sign, exponent and mantissa fields and one rule falls out: the exponent buys range, the mantissa buys precision. From there — why bfloat16 was invented, why FP8 ships in two flavours, and what integer quantization actually destroys. Ends with which format to pick for training versus inference, and how to notice degradation before your users do.
53
·Computer Architecture·★ MEMBER·9 min read
The Memory Wall from Scratch — Why Moving Data Costs More Than Computing
Multiplying two numbers is cheap; delivering them is not. Starting from the physics of charging a wire, we get to why DRAM latency never shrank, the orders of magnitude in the memory hierarchy, Little's law, machine balance and the roofline — and end with a procedure for deciding whether your kernel is compute bound or bandwidth bound.
54
·Computer Architecture·★ MEMBER·9 min read
The Memory Wall from Scratch — Why Moving Data Costs More Than Computing
Multiplying two numbers is cheap; delivering them is not. Starting from the physics of charging a wire, we get to why DRAM latency never shrank, the orders of magnitude in the memory hierarchy, Little's law, machine balance and the roofline — and end with a procedure for deciding whether your kernel is compute bound or bandwidth bound.