EDA Tools from Scratch — Chips Are Written in Software

Nobody hand-places the tens of billions of transistors on a leading-edge chip. Designers write text (RTL), and software compiles it into physical geometry through synthesis, place-and-route, and verification. Here is that pipeline from zero, plus why Synopsys and Cadence became impossible to route around.

A chip is written, not drawn

Say "chip design" and most people picture an engineer drawing microscopic wires one at a time. Until the 1970s that was roughly true. Designers drew polygons on graph paper, and those drawings became the photographic masters.

Not anymore. A leading-edge chip carries tens of billions of transistors; even at one per second, a single person would need centuries. So designers write text instead of shapes. "On the rising edge of the clock, add a and b and store the result in register c" — software translates that sentence into logic gates, maps it onto off-the-shelf parts, assigns coordinates on silicon, connects everything with metal, and emits geometry for the factory. That software stack is called EDA (Electronic Design Automation).

Modern chips, in other words, are written in software and compiled by software. It is exactly the relationship a programmer has with C and machine code. The difference is that the output is not an instruction stream but physical geometry burned into silicon — and once burned, it cannot be patched.

Why hand work is not merely slow

At the heart of chip design sits the placement problem: assign n components to n available sites on the die. Counted naively, that is $n!$ arrangements. With just 20 components you already have about $2.4 \times 10^{18}$ possibilities — checking a billion per second would still take decades. Real chips have millions to hundreds of millions of components. Routing is no kinder: "connect a given set of points with the shortest possible wiring" belongs to the family of problems complexity theory says we cannot solve exactly at scale — the same exponential wall covered in what NP-completeness really means.

So EDA tools abandon optimality by design. Simulated annealing, gradient descent, and divide-and-conquer are stacked in enormous quantity so a problem far beyond human reach lands at decent quality in practical time. The gap between a strong tool and a weak one is the size of that "decent" — and it shows up directly as clock frequency and power on the finished chip.

The pipeline: from RTL to GDSII

Design is a chain of translations, each one dropping a level of abstraction. Learn the name of the artifact handed between stages and industry conversations suddenly become readable.

1. RTL description — behavior written in Verilog / VHDL / SystemVerilog
2. Logic synthesis — RTL becomes a netlist: a connection list of prebuilt parts (standard cells)
3. Place and route (P&R) — every cell gets coordinates on the die, then metal wires connect them
4. Verification and signoff — is the logic right, does it meet timing, does the geometry obey manufacturing rules
5. Tapeout — final geometry (GDSII / OASIS) goes to the fab and gets written onto photomasks

Step 4 is not a stage so much as a background process: it runs alongside 1 through 3 from the first day to the last. It is also where most of the people and most of the compute go.

Stage 1: RTL — describing circuits as behavior

RTL stands for Register Transfer Level: you describe the circuit at the granularity of "which register's value moves to which other register, through what operation."

module accumulator (
  input  logic        clk, rst_n,
  input  logic [15:0] din,
  output logic [15:0] sum
);
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) sum <= 16'd0;
    else        sum <= sum + din;   // accumulate every clock
  end
endmodule

It looks like software, and two things make it emphatically not. First, everything happens at once: a hundred always_ff blocks do not run top to bottom, they all fire together on the clock edge, so line order carries no execution order. Second, what you can write and what you can build are different sets — some constructs simulate happily but cannot be turned into gates, and that boundary is called the synthesizable subset.

Stage 2: Logic synthesis — turning prose into a bill of materials

The synthesis tool rewrites your RTL as a combination of parts from a standard cell library — the catalog a foundry publishes saying "on this process, these are the gates you may use." Two-input NANDs, flip-flops, and hundreds more, each characterized with measured area, delay, and power in a file called Liberty (.lib). Synthesis is, in words, code generation against an instruction set.

What the designer supplies is constraints: conditions like "the clock runs at 1.2 GHz," written in SDC (Synopsys Design Constraints) format. The tool then spends strong high-drive cells on tight paths and small low-power cells on relaxed ones. A path you forgot to constrain is a path nobody optimized — the most common synthesis accident, and it surfaces silently as performance that never arrives.