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The Physics of Power — Why Lowering Voltage Pays So Much

Derive what one switching event costs, then read the dynamic power equation to see why voltage alone enters squared. From there: Dennard scaling and its end, the 60 mV/decade thermodynamic floor, dark silicon, and the resulting turn toward fixed-function circuits and low precision — ending with the arithmetic of what inference costs to run.

ModalitytextTaskhardware

What one switching event costs

A CMOS circuit draws almost nothing while it sits still. It draws current at the instant a state changes. So any discussion of power should start with the question: what does one transition cost?

The output of a logic gate drives the gate capacitance of the next stage plus the wire; call the total CC. Driving that output from 0 to 1 means charging CC up to the supply voltage VV. The supply pushes out charge Q=CVQ = CV and therefore does work QV=CV2QV = CV^2. But what ends up stored in the capacitance is only

Estore=12CV2E_{\text{store}} = \tfrac{1}{2} C V^2
(1)

Put in words: what is parked in the capacitance is capacitance times voltage squared, halved. Double the voltage and one charging event moves four times the energy — that square governs everything that follows. And of the CV2CV^2 the supply paid out, only half of it is sitting there.

The other half is dissipated as heat in the resistance of the charging transistor. Then, on the way back down to 0, the stored 12CV2\tfrac{1}{2}CV^2 is dissipated in the discharge path. One full up-and-down round trip turns CV2CV^2 into heat. Lowering the resistance does not save that half (charging slowly would — but charging slowly means being slow).

The dynamic power equation

To get heat per second, multiply the energy of one round trip by how often transitions happen. With clock frequency ff and an activity factor α\alpha — the fraction of nodes that actually toggle per clock — we get

P=αCV2fP = \alpha C V^2 f
(2)

Read in words, that is a product and nothing more: how many nodes moved, times what one move costs, times how often moves happen. Halve any factor and the heat falls with it — with one exception.

α\alpha measures how much circuitry is thrashing, CC is the total capacitance being driven, VV is the supply voltage, ff is the clock. What matters here is that of the four terms, only voltage enters squared. Halving the frequency halves the power; halving the voltage cuts it to a quarter.

That is why low-power design reaches for voltage first. But the story does not end there.

Lower the voltage and the circuit slows down

Charging a capacitance CC with a current II takes about tdCV/It_d \approx C V / I. Voltage sits in the numerator, so naively a lower VV should be faster — less charge to move. The denominator wins, though. The current a MOSFET can drive when it is on goes roughly as

Ion(VVth)βI_{\text{on}} \propto (V - V_{th})^{\beta}
(3)

Said in words: what opens the tap is not the voltage itself but how far it overshoots the threshold — and because the exponent is above one, halving that overshoot costs you more than half the current.

VthV_{th} is the threshold voltage at which a channel starts to form, and the exponent β\beta runs about 1.2–1.3 in small transistors, nearer 2 in large ones. What sets the current is not VV but the headroom VVthV - V_{th}, so as VV approaches VthV_{th} the drive current withers and delay explodes.

Lower the voltage, then, and you must also lower the frequency. Doing both dynamically according to load is DVFS (dynamic voltage and frequency scaling), present in everything from phones to servers. In the regime where ff tracks VV roughly proportionally,

PV2fV3P \propto V^2 \cdot f \propto V^3

The cube is a compounding rather than a new mechanism, which says that lowering the voltage shrinks what each transition costs and, because the clock has to come down with it, how many transitions fit into a second.

Voltage effectively enters cubed. Drop it by 20% and power nearly halves. Read backwards: raising voltage to squeeze out clock speed makes power rebound cubically. That is the price of a turbo mode.

FIG 1Watch one thing here — what governs how fast a curve climbs is the exponent, not the coefficient. Read the O(n) line as frequency and the O(n²) curve as voltage, and you can see why shaving the same fraction off each pays so differently. The further right the slider goes, the wider the gap between linear and squared

Power and energy are not the same thing

Here is the confusion worth clearing up. PP is heat per second, but what shows up on the electricity bill for a given job is total energy. Halve the frequency and power halves — but the job now takes twice as long, so the energy is unchanged.

Eop=αCV2E_{\text{op}} = \alpha C V^2
(4)

The same statement in words: what one operation costs is fixed by how many nodes moved, the capacitance they drive and the square of the voltage. How many seconds it took is not on the price tag.

Energy per operation contains no ff at all. Dropping the clock alone does not reduce energy; only dropping the voltage does (and you drop the clock in order to drop the voltage). Without that distinction, "we downclocked and the power bill didn't move" is inexplicable.

Leakage current, meanwhile, accumulates with time, so running slower means leaking for longer. Between that and the voltage term there is a boundary: a regime where finishing fast and going to sleep (race-to-idle) wins, and a regime where running slowly at low voltage wins. The optimum is somewhere in the middle, never at either extreme.

So why couldn't we simply keep lowering the voltage? That is the real subject.

Miniaturization once came with a golden rule and no unpleasant side effects. Scale dimensions by , scale the supply voltage by as well, and raise doping by , and the quantities move like this.

What's behind this

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