Mapping the Semiconductor Supply Chain — From Sand to Chip, Who Holds What

One pass through the whole chain that makes a chip — design (EDA/IP), equipment, materials, foundry, OSAT — and why nearly every stage collapses to a handful of firms, read through two formulas: chain availability and HHI.

One chip, dozens of countries shaking hands

The chip in your phone, or in the GPU running your training job, was not "made" in a single factory. The design software comes from the US, the instruction set from the UK, the lithography scanner from the Netherlands, the photoresist from Japan, the wafer from Japan, Taiwan and Germany, the fabrication from Taiwan, the packaging and test from Taiwan, China and Southeast Asia. A single component crosses borders many times before it exists.

What is strange about this chain is that almost every stage has only a handful of players. A car needs screws, and screws have suppliers everywhere. The chip chain instead has several knots where, if one node stops, chips stop worldwide.

This article walks from sand to chip stage by stage and draws a map of where the concentration sits and why it forms there. The physics of manufacturing itself lives in How a Chip Is Made; here the focus is on who holds what.

The map: five stages

1. Design (EDA, IP) — draw the circuit in software, license ready-made building blocks
2. Equipment — build the machines that transfer that drawing onto matter
3. Materials (wafers, chemicals, gases) — supply the matter being written on
4. Front end (foundry / IDM) — build transistors and wiring on the wafer
5. Back end (OSAT, test) — dice the wafer, seal the die in a package, sort the good ones

The arrows do not point one way. Foundry constraints feed back into design rules; packaging constraints tie down the floorplan long before tape-out. A single upstream supplier's constraints decide downstream design choices — that two-way coupling is what makes this chain different from ordinary procurement.

Stage 1 — Design: EDA and IP as invisible infrastructure

A leading-edge chip holds tens of billions of devices. Nobody draws that by hand, so design happens inside EDA tools: logic synthesis, place and route, timing closure, physical verification (DRC/LVS), and the final sign-off checks before manufacturing. The entire flow runs on software from a few vendors — in practice Synopsys, Cadence and Siemens EDA.

The second layer is IP. Almost nobody designs CPU cores, memory controllers or high-speed I/O from scratch; they license proven blocks and assemble them. Arm's instruction set is the de facto standard in mobile CPUs, and RISC-V emerged as the open alternative to it.

The interesting part is that this layer concentrates even though it has no factories and no inventory. Two forces do it: tools are tightly bound to process qualification, which makes switching enormously expensive, and a proven IP block is bought as much for its track record — that is, for lowered risk — as for its function.

Stage 2 — Equipment: machines only one company can build

Deposition, etch, clean, ion implantation, planarization (CMP), metrology — each category has a few suppliers, with names like Applied Materials, Lam Research, Tokyo Electron and KLA.

The most famous knot in the entire chain is the EUV scanner. Only ASML manufactures machines that use 13.5 nm extreme ultraviolet light in volume, and there is no substitute. Each tool contains hundreds of thousands of parts, and those parts — the light source, the multilayer mirrors, the precision stages — are themselves concentrated among specialist suppliers. ASML, in other words, depends on its own upstream oligopolies. How the tool works, and why it is this hard, is covered in EUV Lithography.

Stage 3 — Materials: unglamorous and irreplaceable

Materials cost far less than equipment, and stop production just as completely.

• Silicon wafers: Shin-Etsu, SUMCO, GlobalWafers, Siltronic and a few others; high-grade 300 mm wafers narrow the field further
• Photoresists and process chemicals: heavily Japanese, and EUV resists in particular take years to develop
• Specialty gases: neon for excimer lasers long came disproportionately from Ukraine, and prices spiked with the 2022 disruption
• Raw minerals: as with China's 2023 export controls on gallium and germanium, the feedstock end also serves as a policy instrument

The real reason materials are hard to swap is not the supplier count but requalification. Change one resist and the exposure, etch and clean conditions all shift with it; proving that yield returns takes months to years. That qualification cost is the actual barrier to entry.

Multiplication in series: why concentration is dangerous

Let $a_i$ be the probability that stage $i$ is supplying normally. Then the probability that the whole chain is running is:

$A$ is the availability of the chain, $\prod$ means "multiply all of these together", and $n$ is the number of stages. In plain words: if any single stage stops, everything stops, so the overall probability is the product of the per-stage probabilities. A stage with alternative suppliers pushes $a_i$ toward 1; a sole-sourced stage sets $a_i$ as the ceiling for the entire chain.

Multiplication is harsher than intuition suggests. At 99% per stage, five stages give about 95%, but fifty stages give about 61%. Each link is excellent, and the chain is fragile. It is the same shape as the per-step yield product in How a Chip Is Made.

So how do you measure concentration itself? Industrial organization uses the HHI (Herfindahl–Hirschman Index): square each market share $s_i$ (between 0 and 1) and add them up.

$\sum$ means "add all of these up". Read plainly: squaring before summing counts big players with extra weight. Ten equal firms give $10 \times 0.1^2 = 0.1$; a single monopolist gives $1^2 = 1$. Because of the square, the more lopsided the shares, the faster the number climbs.

def hhi(shares):                      # shares sum to 1
    return sum(s * s for s in shares)

def chain_availability(a):            # per-stage supply availability
    out = 1.0
    for x in a:
        out *= x
    return out

print(hhi([0.6, 0.25, 0.15]))         # a concentrated stage
print(chain_availability([0.99] * 50))

HHI tells you how lopsided a given stage is; chain availability tells you how many lopsided stages sit in series. What makes semiconductors unusual is that high-HHI stages appear all along the chain, one after another.

Stage 4 — Foundry: the wall of capital

The split between design and manufacturing — fabless plus foundry — is now the default. NVIDIA, AMD, Qualcomm and Apple own no fabs and contract manufacturing to foundries such as TSMC. IDMs that design and manufacture in-house (Intel, Samsung, the memory makers) still exist alongside them.

In leading-edge logic, TSMC holds a dominant position with Samsung Foundry and Intel Foundry chasing it. Mature nodes — the generations used for automotive and analog parts — offer more choices such as UMC, GlobalFoundries and SMIC. The closer to the leading edge, the fewer the options: that is the defining property of this stage.

The cause is capital plus the learning curve. A leading-edge fab costs on the order of ten billion dollars or more to build, an EUV scanner costs in the hundreds of millions, and the know-how to ramp yield accumulates only in companies that have actually run volume production. You need to be running to collect the data, and only those with the data can attempt the next node. Memory shows the same pattern: DRAM is effectively three companies (Samsung, SK hynix, Micron), and HBM for AI accelerators is narrower still.

Stage 5 — Back end: the last gate became a new chokepoint

A finished wafer is not yet a product. Dicing, mounting into a package, sealing, and testing to sort good units — that work belongs to OSATs (outsourced assembly and test providers) such as ASE, Amkor and JCET, concentrated geographically in Taiwan, China and Southeast Asia.

This stage rose in importance because advanced packaging now determines performance. In 2.5D and 3D assemblies that place several dies and stacked memory into one package, the package itself becomes a high-performance wiring board. The fact that AI accelerator supply was at times limited by packaging capacity showed that this is no longer merely a finishing step (see Advanced Packaging).

There are knots here too. The build-up film used in package substrates comes from very few suppliers, and few manufacturers can produce the large substrates that big packages need. Automated test equipment is essentially Advantest and Teradyne. The tail of the chain has the same shape of concentration as the head.

Why every stage concentrates

The circumstances differ by stage, but the outcome rhymes. Four forces do the work:

1. Capital intensity: fabs, tools and R&D all demand investment at a scale that blocks entry
2. Learning curve: only companies in volume production accumulate the data, so the gap compounds
3. Tight coupling: equipment, materials and process are co-developed; no piece performs alone
4. Qualification cost: switching a supplier costs the buyer months to years of revalidation

None of these are anyone's malice; they are technical consequences, which is exactly why policy cannot dissolve them quickly. National chip acts, subsidies, fab incentives and export controls are all positioning moves that take this structure as given.

How this plays out on the job

• Procurement and supply-chain engineers expand the bill of materials into a "stage × number of suppliers" table and flag every single-sourced line. Before price, they look at where $a_i$ is pinned to one company and at that stage's lead time. Semiconductor lead times run in months, and you cannot redesign after the order is placed.
• Hardware designers use this map during part selection. Choosing the part that is optimal on paper but sole-sourced hands that one supplier control over your product's lifetime. In practice, second-source availability becomes a selection criterion, with a footprint-compatible alternate held in reserve.
• Design teams using a foundry are bound to specific combinations of PDK (process design kit) and EDA tool versions. Upgrading a tool changes sign-off results, so a version bump right before tape-out is how accidents happen.
• The trap is assuming inventory protects you. The further upstream, the slower the response: a squeeze in materials or equipment reaches finished goods several quarters later. Conversely, when demand falls every stage cuts orders at once and inventory balloons — the bullwhip effect. The volatility of this industry comes from the long serial structure itself.
• A common question is "where is the real single point of failure in this product?" The path to an answer: decompose the BOM by stage, lay out HHI and lead time for each, and name the one place where the multiplication bites.

Summary

• The chain runs design (EDA/IP) → equipment → materials → front end → back end in series, with a handful of players per stage
• Chain availability is a product, $A = \prod a_i$; the sole-sourced stage sets the ceiling for everything
• HHI measures lopsidedness, and semiconductors are unusual in stacking high-HHI stages in series
• Concentration comes from capital intensity, learning curves, tight coupling and qualification cost — none of which move quickly

For the inside of each stage: manufacturing in How a Chip Is Made, the scanner in EUV Lithography, and sealing and assembly in Advanced Packaging. With the map in hand, the details start to explain themselves.