2026-08-12·FREE·9 min read

MOSFETs from the Ground Up — A Sluice Gate Opened by Voltage, and the Reality of Leakage

The switch that fills every CPU and GPU, assuming no prior knowledge. From the sluice-gate analogy to threshold voltage, then the subthreshold leakage equation and why shrinking a transistor makes it leak more — the root of the power problem in one article.

#mosfet #semiconductor #transistor #leakage #hardware

ModalitytextTaskhardware

Inside a chip there are tens of billions of switches

Zoom far enough into the processor in a phone, or into a GPU training an AI model, and you find one single component tiled everywhere. It is called a MOSFET (metal-oxide-semiconductor field-effect transistor), an electrical switch. Addition, matrix multiplication, ChatGPT's inference — in the end every one of them reduces to the order in which these switches are turned on and off.

But this switch is not an ideal switch. Current leaks through it even when it is supposed to be off. That leak is why a phone battery drains while it sits idle, part of what a data center pays for electricity, and the reason a golden rule that held for decades — shrink the transistor and you get speed and low cost — fell apart. This article builds up how a MOSFET works from nothing, then goes all the way to why it leaks and why shrinking it makes the leak worse.

The analogy: a sluice gate opened by voltage

A MOSFET has three terminals. In terms of a waterway they are:

Source: where the water comes in
Drain: where the water goes out
Gate: the sluice gate standing partway along the waterway

Normally the channel between source and drain is blocked with earth, and no water (current) flows. Apply a voltage to the gate and the sluice opens, the waterway connects, and water flows. Cut the voltage and the sluice closes. That is the basic action of the switch.

This sluice gate has one virtue that no mechanical switch has: almost no current flows into the gate itself. Opening and closing it consumes no water. Because control is nearly free, you can line up tens of billions of them without the cost of control collapsing.

The gate has a weak point too: it never closes completely. Shut it and water still seeps slowly through the gap underneath. That seepage is the analogy for the main subject of this article, leakage current.

How it works: three terminals and one insulating film

Now replace the analogy with the real thing. In a p-type silicon substrate — land where electrons are scarce — embed two n-type regions, which are rich in electrons, a short distance apart. Those are the source and the drain. On the surface between them, grow an extremely thin insulator called the gate oxide, and place an electrode on top of it. That electrode is the gate.

Apply a positive voltage to the gate and the field reaching through the insulator pulls electrons inside the substrate toward the surface. Once enough electrons have gathered, a path for electrons connecting source and drain — the channel, or inversion layer — forms at the surface, and current starts to flow. Because the gate is held apart by the insulator, it only attracts electrons and passes no current itself. This insulating film is what actually lies behind "opening and closing the sluice gate consumes no water."

Here the most important parameter of all appears. The gate voltage at which the channel begins to form is called the threshold voltage $V_{th}$ . The textbook version reads "above $V_{th}$ it is on, below it is off" — but reality is not that tidy.

A real switch is not a staircase

For an ideal switch, a plot with gate voltage on the horizontal axis and current on the vertical would be a staircase: at $V_{th}$ the current leaps from zero. Measure a real device, however, and the rise is a smooth curve — below the threshold, the current never becomes exactly zero. The current in this region is called the subthreshold current, and it follows the equation below.

I_D \approx I_0 \, \exp\!\left(\frac{V_{GS}-V_{th}}{n\,V_T}\right)

(1)

Here is the same statement in words: the drain current $I_D$ shrinks exponentially with how far the gate voltage $V_{GS}$ sits below the threshold $V_{th}$ — it gets small, but it does not get to zero. That exponential is a claim about ratios rather than amounts, which says: take the gate voltage down by another equal step and the current is divided by the same factor again, so it keeps dividing its way toward the floor without ever landing on it. The remaining symbols fill in the details — $I_0$ sets the scale of the current near threshold, $V_T = kT/q$ is the thermal voltage (Boltzmann constant × absolute temperature ÷ elementary charge, about 26 millivolts at room temperature), and $n$ is a factor of roughly 1 to 1.5 determined by the device structure.

Why does it leak? At the entrance of the channel sits an energy barrier that holds electrons back, but electrons are constantly being shaken by heat, and a statistically fixed fraction of them simply climbs over the barrier. Close the gate and the spray still comes over if the water is choppy — and the height of the waves, the temperature, is not something a circuit designer controls.

The slope of this leak is expressed by the subthreshold swing $S = n V_T \ln 10$ , which means "the gate voltage needed to cut the current by a factor of ten." Substitute the room-temperature $V_T$ into equation (1) and even the ideal case of $n=1$ gives about 60 millivolts per decade. This is a floor imposed by thermal statistics itself, which no material or trick can break (for an ordinary transistor, that is; there is research into tunnel FETs and other devices that change the operating principle outright in order to break the floor).

FIG 1An ideal switch is a staircase, but a real transistor turns on as smoothly as this sigmoid. Drag the input (which stands in for gate voltage) below the threshold and the output only gets smaller — it never reaches zero. That tail is leakage current

Why it leaks more the smaller it gets

From the 1970s onward the semiconductor industry rode a golden rule known as Dennard scaling: when you shrink a transistor's dimensions, bring the supply voltage and the threshold voltage down by the same ratio. Speed then rises while power density — the heat generated per unit of area — stays constant. It is a dream equation in which the smaller you make things, the faster and cheaper the chip gets without drawing more electricity.

What broke that equation is the expression we have just derived. Leakage current in the off state ( $V_{GS}=0$ ) depends exponentially on $V_{th}$ . In other words, every 60 to 90 millivolts you shave off the threshold voltage multiplies leakage by ten. And the thermal voltage $V_T$ in the denominator is fixed by physical constants and temperature, so it does not scale however small the transistor becomes. The dimensions can be shrunk; the tail of the exponential cannot.

As a result, by the middle of the 2000s the reduction of $V_{th}$ had effectively stopped, dragging the reduction of supply voltage to a halt with it. Since only the dimensions kept shrinking, power density turned upward, and we entered the age of dark silicon — run the entire chip at full tilt at once and it burns. CPU clocks topping out near 4 GHz and the turn toward multicore, and GPU performance coming to be discussed in terms of operations per watt, both lead back to this exponential when you trace them to the source. The physics of power covers that connection in detail.

Shrinking opened other leakage paths as well.

Tunneling leakage through the gate oxide: keeping the field strong meant thinning the oxide further and further, until its thickness reached a few atoms and electrons began to slip straight through the insulator by quantum tunneling. This is why the late 2000s saw a generational shift to high-permittivity (high-k) materials, which make a film that is electrically thin and physically thick.
Short-channel effects: bring source and drain too close together and the drain's high voltage pulls the barrier down from the side (DIBL), and the gate loses its grip. Standing the channel up as a fin and squeezing it from three sides with the gate (FinFET), then wrapping it all the way around (GAA, gate-all-around), is the fight to win that grip back.

Getting a feel for it in code

Hammer equation (1) into a calculator and the severity of the trade-off shows up as numbers.

import numpy as np

VT = 0.026                   # thermal voltage kT/q (room temperature, volts)
n  = 1.4                     # subthreshold factor
S  = n * VT * np.log(10)     # about 84 mV per decade

def off_current(vth):        # leakage at Vgs=0 (relative)
    return 10 ** (-vth / S)

for vth in [0.45, 0.35, 0.25]:
    print(f"Vth={vth:.2f}V  leakage x{off_current(vth)/off_current(0.45):.0f}")

Take the threshold from 0.45 V down to 0.25 V — a mere 0.2 V, given up to make the switch faster — and the off current grows by roughly 240×. If you want speed, you pay in leakage. That this exchange rate is exponential is the starting point of all low-power design.

How this plays out in practice

Physical designers of digital circuits handle this trade-off most routinely of all. A standard cell library ships the same logic gate in several multi-Vt flavors (HVT, SVT, LVT and so on, differing in threshold), and the synthesis and place-and-route tools swap in the fast LVT cells only on paths with tight timing, then put paths with slack back on HVT to cut leakage down (leakage recovery). What the designer actually looks at is the leakage tables in the cell library (.lib), the tool's leakage optimization options, and the corner setup at signoff.

The pitfall is confusing temperature with corners. Since $V_T$ in equation (1) is proportional to temperature, leakage grows exponentially when things get hot. Verify timing at the slow corner (SS, low voltage) but estimate leakage from the room-temperature typical value, and you get an accident where standby current on hot hardware blows several times past the budget. Always estimate leakage at high temperature and the FF corner. For an embedded device, keep in mind that the "typ" sleep current on the datasheet assumes 25 °C — in automotive or outdoor installations the figure can shift by an order of magnitude.

In low-power design, the standard approach is not to reduce leakage but to cut off the power supply itself, that is, power gating. Define power domains in a format such as UPF or CPF and disconnect unused blocks with switches. Forget the retention design that holds state across the shutdown, and data vanishes every time the block goes to sleep.

A stock interview question is worth mentioning too: "Why can't supply voltage keep coming down?" The line of reasoning in the answer is this article itself. Holding onto speed requires dropping $V_{th}$ along with the supply voltage, but leakage rises exponentially with $V_{th}$ . That slope has a thermal-statistics floor of one decade per 60 mV at room temperature, which neither materials nor process can break. So voltage scaling stopped, and power became the ceiling on performance — get that far in one breath and it is enough.

Summary

A MOSFET is a "sluice gate opened by voltage." Because the gate is insulated, the act of controlling it draws almost no current
It turns on around the threshold voltage $V_{th}$ , but not as a staircase — it trails the tail of an exponential. At room temperature, 60 mV per decade is the theoretical floor
Lowering $V_{th}$ buys speed but multiplies leakage exponentially. Because thermal voltage does not scale, voltage scaling stopped as dimensions kept shrinking, and power became the wall in front of performance
As countermeasures against oxide tunneling leakage and short-channel effects, the structure has evolved through high-k dielectrics, FinFET, and GAA

If you would like to follow the structure and operation of the transistor slowly, with figures, head to Chapter 4 of the textbook, "MOSFET — A Sluice Gate Opened by Voltage". For how the physics of this switch connects to the power of the whole chip, the physics of power is the sequel; for how arithmetic and data movement compete on top of that chip, it is the memory wall.