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Thermal Design from Scratch — The Wall in 3D Stacking Is Heat

Nearly all the power that enters a chip leaves it as heat. Temperature is set by a series stack of thermal resistances, and once you stack dies vertically the hottest layer heats up with the square of the layer count. Heat flux and hotspots, the lag that thermal mass introduces, and which term liquid cooling actually removes — picking up where the power budget left off.

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Power becomes heat that has nowhere else to go

Almost all of the electrical energy that enters a chip comes back out as heat. It does not turn into light or sound, and it moves nothing outside the package. Even the part sent off as a signal to a neighbouring chip ends up charging and discharging wires over there, and becomes heat too. So "700 watts of power" can be read, with no meaningful loss of accuracy, as "a 700-watt heater."

The difference from an actual heater is the size of the element. A space heater spreads a few hundred watts over an area the size of a small rug; an accelerator emits the same or more from something closer to a postage stamp. The same wattage is far harder to deal with when it leaves through a small window. Nearly everything in thermal design follows from that.

Cooling, then, is not a spell that lowers temperature. It is the work of pushing heat that was born inside the die out to a dumping ground — air or water. If you push it out as fast as it appears, the temperature settles at some value; if you do not, it climbs. Predicting where it settles is what the rest of this article is about.

The intuition: temperature is a measure of congestion

Heat maps cleanly onto an electrical circuit. Treat the heat flow PP (watts) as current, the temperature difference ΔT\Delta T (°C) as voltage, and how hard it is for heat to get through, θ\theta (°C/W), as resistance.

ΔT=Pθ\Delta T = P \cdot \theta
(1)

In words: how hot something gets is how much heat it is pushing, times how congested the route out is. Here PP is the heat the chip is producing and θ\theta is called thermal resistance — how many degrees of difference appear per watt you push through. The unit carries the meaning, so read °C/W as "the markup per watt."

This analogy is not a pun. Fourier's law of heat conduction says heat flows in proportion to the temperature difference, which is structurally the same statement as Ohm's law. So the familiar bookkeeping — resistances in series add, resistances in parallel divide — carries over unchanged.

Thermal resistances add in series

Lay out the actual path from the transistors to the outside air.

Junction (the layer where the transistors live) → silicon substrate → thermal interface material (TIM) → metal lid → a second TIM → heat sink or cold plate → air or water.

Every segment of that one-way road has a θ\theta, and because they sit in series, they simply add.

Tj=Ta+PiθiT_j = T_a + P \sum_i \theta_i
(2)

That is: transistor temperature equals ambient temperature plus the heat being dissipated times the total congestion of the route. TjT_j is the junction temperature (the temperature where the transistors actually are), TaT_a is ambient, and each θi\theta_i is one segment's thermal resistance.

What makes this interesting is how far apart materials sit in thermal conductivity. Copper is around 400, silicon around 150, thermal greases somewhere between 1 and 5, and air about 0.03 W/(m·K). Three or four orders of magnitude. The consequence is an inversion you meet constantly: a tenth of a millimetre of grease can present more thermal resistance than several millimetres of solid copper. "It is thin, so ignore it" simply does not hold here.

And because the terms add, the largest one runs the show. Doubling the heat sink barely moves the temperature if the TIM is the dominant term. Deciding what to fix means first producing the itemised list — exactly the discipline of measuring before optimising performance.

Stack the dies and temperature grows with the square

Now the main event. There is a limit to how far a chip can spread out in the plane, so the industry went vertical for bandwidth and wire length (Advanced Packaging covers that process).

Electrically, stacking is nothing but good news: shorter wires, more bandwidth, less energy per bit moved. Thermally, the story is completely different.

There are two reasons. First, stacking multiplies the heat but not the exits. You can attach a cooler to one face of the stack, and that face does not get bigger as you add layers. The second reason is nastier: heat from the layers far from the cooled face has to travel through every layer in front of it.

FIG 1Read the straight line as "total heat as layers are added" and the parabola above it as "temperature rise of the layer furthest from the cooled face." Push the horizontal axis — think of it as layer count — to the right and the gap opens far faster than the heat itself grows. Switch to a log scale and only the difference in slope survives. Why it turns out to be a square is counted out just below

Let us count. Suppose layers each dissipate , and the thermal resistance between adjacent layers is . The heat crossing the -th interface counted from the cooled face is the sum of everything behind it, so . The temperature rise of the furthest layer is the sum over every interface it must cross.

What's behind this

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