Reading Chip Design as a Power Budget — The Physics of Leakage and Heat

A modern chip is limited not by what fits, but by how much of it can be lit at once. This piece reads that limit as a household budget: dynamic power versus leakage, the positive feedback that makes leakage swell with temperature, the thermal resistance that converts watts into degrees, and the three — and only three — ways a designer can spend the watts.

The House Whose Breaker Was Already Sized

Picture chip design as a house on a fixed electrical contract. You can add rooms — silicon area — more or less freely, but the breaker, meaning the heat your cooling can actually carry away, does not grow with them. Run the air conditioner, the microwave, and the dryer at once and it trips. So the occupants stop asking what to put in the house and start asking what may run at the same time.

That is exactly where modern chips sit. Each process generation hands you more transistors, while the heat you can remove is set by the package and the cooling loop and barely moves. The subject of a design conversation shifted from area to watts — arguably the biggest change of the past two decades.

So a designer's first document is a budget sheet. Decide the total watts available, then allocate them: to the cores, to the caches, to the memory interfaces, to the I/O. That sheet is the power budget, and this article is about how to read it.

Two Kinds of Spending — Metered and Fixed

The heat a chip produces splits into two line items that behave nothing alike.

Read in words, the bill is a metered charge for every switching event plus a standing charge you pay merely for keeping the power on. Here $\alpha$ is the fraction of circuits that actually toggle per clock, $C$ the capacitance being driven, $V$ the supply voltage, $f$ the clock frequency, and $I_{\text{leak}}$ the current that seeps through transistors that are supposedly off.

Why the first term carries $CV^2$, and why voltage alone enters squared, is derived in The Physics of Power. What matters here is the second term. Leakage burns power while no work is being done. That is why an idle chip is warm, and the standing charge scales with transistor count: billions of devices, all quietly seeping at once.

Seen as a budget, the two demand opposite tactics. Metered spending falls when you stop doing useless work. The standing charge is indifferent to how busy you are, so the only way to cut it is to remove the power itself.

The Standing Charge Swells on Its Own

The awkward part is that leakage is not a constant. The subthreshold current through an off transistor takes roughly this form:

The exponent is the whole story, which says that leakage falls off exponentially with how high the threshold voltage stands relative to the thermal energy of the electrons. $V_{th}$ is the threshold voltage at which the transistor begins to open, $kT/q$ is the thermal voltage — about 26 mV at room temperature — and $n$ is a factor slightly larger than one.

Note that $T$ is absolute temperature. As the die heats, $kT/q$ grows, the magnitude of the fraction in the exponent shrinks, and leakage rises for no reason other than the heat. On top of that, $V_{th}$ itself drifts downward as temperature rises, so both effects push the same way.

Subthreshold conduction is not the only escape route. As gate dielectrics thinned, current tunneling straight from the gate into the channel stopped being negligible — a problem largely tamed by high-k dielectrics. But the path that swells with temperature is mainly the subthreshold one.

Because the relationship is exponential, its growth defies intuition. Design conversations lean on a coarse rule of thumb — leakage roughly doubling per ten-degree rise — but the true coefficient depends on the process and the operating point. What matters is not the multiplier but the shape. Dynamic power grows as a well-behaved polynomial in voltage and frequency; leakage grows exponentially in temperature and threshold voltage. It is negligible while you have margin, and then it eats the budget all at once.