What Moore's Law Actually Says — What Ended, and What Is Still Going

"Double every two years" was never a law of physics — it was a timetable the industry agreed to keep. Dennard scaling is what ended; cost is what slowed; density and going vertical are what continue. A ground-up tour through log axes, the flat-to-FinFET-to-GAA story, and the arithmetic of cost per transistor.

"Double every two years" was a timetable, not a law

People invoke Moore's Law with the same tone they use for gravity. It is closer to a train timetable. If the train shows up at the same minute every day it starts to look like a fact of nature, but what keeps it on time is not physics — it is that everyone agreed on the schedule and organized themselves around it.

In 1965 Gordon Moore plotted a handful of data points on how many components were fitting onto a single chip and wrote that, for a while yet, the count would keep doubling every year. The version quoted today is his 1975 revision: doubling roughly every two years. What usually gets dropped is what he was actually counting — components, and their economics. More precisely, the level of integration at which the cost per component is lowest. Not speed. Not power.

So why did an offhand observation hold for decades? Because the industry built shared roadmaps around it, and equipment makers, materials suppliers, and design houses all planned their investments against the same cadence. The moment it became a shared target, the prediction turned into a plan. Which is why "is Moore's Law dead?" deserves a question back: dead in which sense — density, power, or cost? The three did not end at the same time, or in the same way.

First, learn to read an exponential

On a linear axis an exponential looks like it crawls along the floor for ages and then leaps up one day out of nowhere. Put the same data on a log vertical axis and it becomes a straight line. Moore's Law charts look like half a century of straight line because the y-axis is logarithmic — and the slope of that line is the doubling time.

This matters in practice more than it looks. Stretch the doubling time from two years to three, and twelve years out you get $2^4=16\times$ instead of $2^6=64\times$. The chart barely changes shape; the hardware you actually get is four times smaller. That is why "it only slowed down a bit" is never a small statement.

The widget below was built to compare growth rates of algorithms, but here just watch the axis toggle.

What actually ended was Dennard scaling

In 1974, Robert Dennard and colleagues at IBM formalized the good deal hidden inside miniaturization: shrink every dimension by $1/\kappa$ and drop the supply voltage by $1/\kappa$ along with it, and the power per unit area stays constant.

The dynamic power of a chip is approximated by:

$\alpha$ is the fraction of circuits that actually switch in a given cycle, $C$ is the capacitance being charged and discharged (how big a bucket of charge you have to fill), $V$ is the supply voltage, and $f$ is the clock frequency. Put in words: every time you flip a switch you pay about $CV^2$ of energy, and you do that $f$ times a second. Note that voltage is the only term that is squared.

Here is the bookkeeping. Shrink by $1/\kappa$ and capacitance falls by $1/\kappa$, voltage falls by $1/\kappa$, and the transistor gets fast enough to run $\kappa$ times the clock. Multiply it out and power per device drops as $1/\kappa^3$, while area drops as $1/\kappa^2$ so you pack $\kappa^2$ more of them into the same space. The two cancel: power density does not rise. Smaller meant faster, cheaper, and no hotter, all at once. That is the era — running until the early 2000s — when moving a design to the next node made the product better with no redesign at all.

The voltage side is where it broke. To lower $V$ you must also lower the threshold voltage $V_{th}$, or the transistor never really turns on. But lowering $V_{th}$ makes the current that leaks while the device is supposedly off grow exponentially — and how fast it grows has a floor set not by materials or cleverness but by thermal statistics:

$k$ is the Boltzmann constant, $T$ the absolute temperature, $q$ the elementary charge — which says that at room temperature you must move the gate voltage by at least 60 millivolts to cut the current by a factor of ten. Flip it around and it says every 60 mV you shave off the threshold multiplies your standby leakage by ten. Where that wall comes from is worked through in MOSFETs from the Ground Up — A Sluice Gate Opened by Voltage, and the Reality of Leakage.

The consequence: by the mid-2000s supply voltages stalled around 1 V and the clock-speed race stopped with them. Performance after that came from core count and specialized circuits. The full power derivation, and the dark silicon it produced (not being able to run every circuit flat out at once because of the power budget), is in The Physics of Power — Why Lowering Voltage Pays So Much. What died was Dennard scaling, not Moore's Law. Density kept climbing; the power budget to switch all of it ran out. That is what happened around 2005.

"5 nm" is no longer a length

There was a time when the number in a node name corresponded roughly to a physical gate length. Not anymore. Nothing on a "3 nm" process measures three nanometers; real gate lengths and wiring pitches are tens of nanometers. The number is a generation label, not a dimension — and two foundries can print the same number at meaningfully different densities.

Look at these instead: transistor density (millions of transistors per mm²), SRAM bit-cell area, and each vendor's published figure for either "same power, more performance" (iso-power) or "same performance, less power" (iso-performance). Always check which of the two a quoted improvement refers to.

Worse, the chip no longer shrinks evenly. Logic still scales; SRAM (the memory used for caches), analog, and I/O barely do. Conference disclosures in recent leading nodes have shown SRAM cell shrink essentially flattening out. That unevenness is exactly what motivates chiplets later on.

Planar → FinFET → GAA: buying time by going vertical

The physical reason shrinking gets hard is that the gate loses control of the channel. In the sluice-gate picture, a planar transistor is a single plate laid over one side of the channel. Make the channel short enough and the plate no longer reaches the far end — the gate is closed and current still slips past. That is the short-channel effect.

The fix was to wrap more sides. First the FinFET: stand the channel up like a fin and surround it on three sides. Intel took it to volume as tri-gate on its 22 nm generation in 2011, and the other foundries followed at 16/14 nm. Next came GAA (gate-all-around, or nanosheet): flatten the channel into thin sheets and enclose it completely. Samsung announced it as MBCFET on its 3 nm generation, Intel calls its version RibbonFET, and TSMC has stated it moves to nanosheets at N2.

The goal is identical in every case: recover the gate's grip so the device can switch at a lower voltage and leak less while off. There is a side effect — with nanosheets you no longer pick channel width continuously, you pick it in whole sheets, so the design knob becomes discrete. Waiting behind this are CFET (stacking n-type and p-type devices on top of each other) and backside power delivery (routing supply wiring on the underside of the wafer). Both are the same move: stop fighting on the plane, escape upward.

The cost curve — shrinking no longer means cheaper by default

Moore's original claim was about cost, so write it out:

In words: how many usable chips come off one disc, and how many switches are on each. The denominator (density) still rises each generation — but lately the numerator rises too. EUV scanners are expensive, multi-patterning adds process steps, mask sets cost more, and design and verification take more people. Both sides climb together, so the net no longer falls as cleanly as it once did.

This is a genuinely unsettled question. One camp holds that cost per transistor has been flat since 28 nm; the other holds that it keeps falling once a node reaches volume. Real cost data is rarely public, and the answer moves depending on production volume, yield, and how you amortize design cost. What both camps agree on is narrower and more useful: you can no longer assume a shrink automatically makes transistors cheaper.

Putting yield into the arithmetic makes it concrete (the numbers below are illustrative):

def cost_per_transistor(wafer_usd, dies_per_wafer, defect_density, die_mm2, mtr_per_mm2):
    yield_ = 1.0 / (1.0 + defect_density * die_mm2)   # simple yield model
    good = dies_per_wafer * yield_                     # dies you can actually sell
    transistors = die_mm2 * mtr_per_mm2 * 1e6          # MTr/mm² → count
    return wafer_usd / (good * transistors)

Try doubling die_mm2. You get half as many dies per wafer and a worse yield on each, so unit cost more than doubles. A big chip costs more than its area suggests. The relationship between defect density and area is covered in How Chips Are Made — From Wafer to Yield.

What is still going: density, stacking, specialization

Density is still increasing. The pace is slower and the doubling time longer, but it has not stopped. GAA and backside power delivery are investments in extending that straight line by a few more generations.

The battleground moved from one die to how you bind several together. Memory stacks DRAM into HBM; flash gave up on the plane and grew layers as 3D NAND; in logic, advanced packaging links multiple dies with short, fat interconnect. What can no longer be won laterally is being won vertically and at the interfaces.

Chiplets became standard practice. The logic is simple: there is no reason to build the parts that don't shrink on the most expensive process available. AMD split compute from I/O across different processes starting with Zen 2. And by the cost equation above, cutting one big die into small ones raises yield while letting each block sit on the node that suits it.

What you spend the transistors on now decides the outcome. A circuit dedicated to matrix multiplication paired with low-precision number formats does far more arithmetic per watt than an equal area of general-purpose ALUs. The shortfall left by slowing lithography is being recovered one level up, in architecture and numerics.

How this shows up in practice

This lands on your desk when you choose hardware, set a power budget, or forecast cost a few years out: datacenter capacity planning, thermal design for edge devices, SoC scoping, estimating inference cost. Every one of them needs an assumption about how much better the next generation gets.

Don't use node names as a performance proxy. A vendor's "N% faster" means something completely different depending on whether it is quoted at iso-power or as iso-performance power savings. Line up density, SRAM area, and which condition the number was measured under before you compare anything.

Your power ceiling is thermal, not spatial. In production, TDP and cooling saturate before area does. When you touch a power cap — nvidia-smi -pl, Intel's RAPL, DVFS settings on embedded parts — keep $P=\alpha C V^2 f$ in mind: dropping the clock a little lets the operating voltage drop too, and voltage enters squared, so consumption falls further than the frequency change suggests.

Don't bake "it gets cheaper every year" into a forecast. Extrapolating three years out with early-2010s intuitions will miss. Always carry a conservative scenario alongside: longer doubling time, cost per transistor roughly flat.

Four ways this bites. Assuming more transistors means more speed — the power budget prevents running everything flat out at once. Treating die size casually — double the area and unit cost more than doubles. Assuming cache capacity grows on schedule each generation — SRAM stopped shrinking, so any performance estimate that depends on the working set fitting in cache can be wrong. Comparing node names across foundries — the definitions are not shared.

When someone in a design review asks whether Moore's Law is over, answer by splitting the term: density continues but has slowed, Dennard scaling ended in the mid-2000s, and cost reduction is at best no longer automatic. Then carry it through to consequences — multicore, then specialized circuits, then chiplets and packaging — and the argument holds together.

Summary

• Moore's Law is not physics. It is an observation about density and economics that the industry turned into a shared plan
• Dennard scaling is what ended in the mid-2000s: threshold voltage and the 60 mV/decade floor stopped voltage from falling
• Node names are no longer lengths. Compare density, SRAM area, and iso-power / iso-performance figures
• Device structure bought time by going vertical: planar → FinFET → GAA
• Still going: density, stacking and packaging, and specialization — the gains moved up a level from the transistor