How Chips Are Made — From Wafer to Yield

Every GPU and phone processor starts as sand and passes through hundreds of printing steps. From the basic moves — lithography, etching, ion implantation — to the brute force of EUV and the yield math that makes big dies exponentially expensive, explained from zero.

Building a City on a Grain of Sand

The processor in your phone and the GPUs that train AI models both pack tens of billions of switches (transistors) onto a chip that fits on a fingertip. Obviously, nobody assembles them one at a time. Chips are printed — by a process remarkably close to developing a photograph, with billions of devices formed in a single pass.

The raw material is ordinary sand (silicon dioxide). The silicon extracted from it is refined to a staggering purity — on the order of one foreign atom per ten billion — grown into a massive single crystal, sliced thin, and polished to a mirror finish. The result is a 300mm wafer, and every chip in the world begins life on one of these discs.

This article follows the journey from wafer to chip from first principles: the basic moves of manufacturing (lithography, etching, ion implantation), then the brute-force technology called EUV, and finally the mathematics of yield — the numbers that decide whether a semiconductor business lives or dies.

The Metaphor: A Woodblock Print with 100 Layers

Picture a multi-color woodblock print. Each color gets its own carved block, and the blocks are pressed onto the same sheet one after another. If a single layer lands out of place, the picture is ruined.

A chip is exactly this: a print with dozens of layers. Each layer repeats the same cycle — coat with a light-sensitive material, expose the pattern, carve, clean. The only difference is precision. Where a woodblock print might tolerate a millimeter of misalignment, the alignment budget between chip layers (overlay) is a few nanometers — less than one ten-thousandth the width of a human hair.

The Big Picture: From Sand to Package

The full journey runs like this:

1. Wafer production: sand → refined silicon → single-crystal ingot → slicing and polishing → 300mm wafers
2. Front end of line (FEOL): building the transistors themselves into the wafer surface
3. Back end of line (BEOL): stacking a dozen or more layers of copper wiring to connect them
4. Test → dicing → packaging: probing on the wafer, cutting it into individual chips (dies), and sealing them

Hundreds of identical chips are built simultaneously on each wafer, arranged in a grid. The whole flow takes several hundred process steps spread over months.

And those hundreds of steps boil down to four basic moves, repeated over and over: coat (deposition), expose (lithography), carve (etching), and inject (ion implantation). Let's walk through the three at the heart of it.

Lithography: Printing Circuits with Light

First the wafer is coated with a thin layer of photoresist, a light-sensitive material. Then ultraviolet light is shone through a master plate carrying the circuit pattern (the reticle) and projected onto the wafer through lenses that shrink it 4×. With a positive resist, only the illuminated regions dissolve in developer, leaving circuit-shaped "windows" in the resist. The next etch will carve exactly through those windows. Lithography, in other words, is making a stencil out of light.

How fine a pattern can we print? The limit is set by the Rayleigh criterion:

$CD$ is the smallest printable feature (the Critical Dimension), $\lambda$ is the wavelength of the light, $NA$ is the numerical aperture — how wide a cone of light the lens can gather — and $k_1$ is a factor for how hard the process squeezes the physics. Read in words, the formula says: the finest line you can print is the wavelength of your light, divided by how much of that light the lens manages to catch, times a factor for how far your process tricks let you push. So there are only three ways to draw a finer line — shorten $\lambda$, widen $NA$, or shave $k_1$. In one sentence: you cannot straightforwardly print features finer than the wavelength of your light.

The longtime workhorse, the ArF excimer laser, has a wavelength of 193nm. Immersion lithography fills the gap between lens and wafer with water to push NA up to 1.35, and multi-patterning splits a pattern too dense for one exposure across two or more masks printed in sequence (effectively lowering $k_1$). Together these squeezed out features under a tenth of the wavelength — but equation (1) is a wall, and pushing further required something drastic.