How Are Chips Made? From Silicon Wafer to Yield, Explained

How chips are made: every GPU and phone processor starts as sand and passes through hundreds of printing steps. From the basic moves — lithography, etching, ion implantation — to the brute force of EUV and the yield math that makes big dies exponentially expensive, explained from zero.

Building a City on a Grain of Sand

The processor in your phone and the GPUs that train AI models both pack tens of billions of switches (transistors) onto a chip that fits on a fingertip. Obviously, nobody assembles them one at a time. Chips are printed — by a process remarkably close to developing a photograph, with billions of devices formed in a single pass.

The raw material is ordinary sand (silicon dioxide). The silicon extracted from it is refined to a staggering purity — on the order of one foreign atom per ten billion — grown into a massive single crystal, sliced thin, and polished to a mirror finish. The result is a 300mm wafer, and every chip in the world begins life on one of these discs.

This article follows the journey from wafer to chip from first principles: the basic moves of manufacturing (lithography, etching, ion implantation), then the brute-force technology called EUV, and finally the mathematics of yield — the numbers that decide whether a semiconductor business lives or dies.

The Metaphor: A Woodblock Print with 100 Layers

Picture a multi-color woodblock print. Each color gets its own carved block, and the blocks are pressed onto the same sheet one after another. If a single layer lands out of place, the picture is ruined.

A chip is exactly this: a print with dozens of layers. Each layer repeats the same cycle — coat with a light-sensitive material, expose the pattern, carve, clean. The only difference is precision. Where a woodblock print might tolerate a millimeter of misalignment, the alignment budget between chip layers (overlay) is a few nanometers — less than one ten-thousandth the width of a human hair.

The Big Picture: From Sand to Package

The full journey runs like this:

1. Wafer production: sand → refined silicon → single-crystal ingot → slicing and polishing → 300mm wafers
2. Front end of line (FEOL): building the transistors themselves into the wafer surface
3. Back end of line (BEOL): stacking a dozen or more layers of copper wiring to connect them
4. Test → dicing → packaging: probing on the wafer, cutting it into individual chips (dies), and sealing them

Hundreds of identical chips are built simultaneously on each wafer, arranged in a grid. The whole flow takes several hundred process steps spread over months.

And those hundreds of steps boil down to four basic moves, repeated over and over: coat (deposition), expose (lithography), carve (etching), and inject (ion implantation). Let's walk through the three at the heart of it.

Lithography: Printing Circuits with Light

First the wafer is coated with a thin layer of photoresist, a light-sensitive material. Then ultraviolet light is shone through a master plate carrying the circuit pattern (the reticle) and projected onto the wafer through lenses that shrink it 4×. With a positive resist, only the illuminated regions dissolve in developer, leaving circuit-shaped "windows" in the resist. The next etch will carve exactly through those windows. Lithography, in other words, is making a stencil out of light.

How fine a pattern can we print? The limit is set by the Rayleigh criterion:

$CD$ is the smallest printable feature (the Critical Dimension), $\lambda$ is the wavelength of the light, $NA$ is the numerical aperture — how wide a cone of light the lens can gather — and $k_1$ is a factor for how hard the process squeezes the physics. Read in words, the formula says: the finest line you can print is the wavelength of your light, divided by how much of that light the lens manages to catch, times a factor for how far your process tricks let you push. So there are only three ways to draw a finer line — shorten $\lambda$, widen $NA$, or shave $k_1$. In one sentence: you cannot straightforwardly print features finer than the wavelength of your light.

The longtime workhorse, the ArF excimer laser, has a wavelength of 193nm. Immersion lithography fills the gap between lens and wafer with water to push NA up to 1.35, and multi-patterning splits a pattern too dense for one exposure across two or more masks printed in sequence (effectively lowering $k_1$). Together these squeezed out features under a tenth of the wavelength — but equation (1) is a wall, and pushing further required something drastic.

EUV: Brute Force at 13.5 Nanometers

EUV (extreme ultraviolet) lithography cuts the wavelength from 193nm to 13.5nm in one stroke — attacking the numerator of equation (1) head-on. The price is staggering.

Merely producing the light is a feat. An EUV source fires tens of thousands of molten tin droplets per second, each a few tens of micrometers across, and hits each one in flight with a high-power laser. The droplet becomes a plasma, and the EUV light it radiates is collected.

Worse, light at this wavelength is absorbed by almost everything — including air and the glass of any lens. So the machine's interior is a vacuum, lenses are impossible, and the light is steered entirely by exotic multilayer mirrors built from dozens of alternating molybdenum and silicon films. Even these lose roughly 30% of the light per bounce; after the ten or so mirrors in the optical path, only a few percent of the light reaches the wafer. Even the mask becomes reflective instead of transmissive. The end of this road is an exposure tool costing hundreds of millions of dollars — an outlier among industrial machines. The industry is now moving to High-NA EUV, raising NA from 0.33 to 0.55.

Etching and Ion Implantation: Carving, Then Changing the Material

Etching removes the film beneath the resist windows opened by lithography. Dipping the wafer in chemicals (wet etching) dissolves material in all directions equally, which ruins narrow, deep features. So fine patterning uses dry etching (reactive ion etching), which accelerates ions in a plasma straight down into the wafer, producing the anisotropy — carving only downward — that deep, skinny trenches demand.

Ion implantation doesn't carve; it changes the electrical nature of the material itself. Impurity ions — boron, phosphorus, arsenic — are accelerated by an electric field and literally shot into chosen regions of the silicon. Where, how deep, and how many determines the n-type and p-type regions, and with them the transistor's electrical personality — for instance the threshold voltage, the "height of the floodgate" that decides when the switch turns on. The bombardment wrecks the crystal lattice, so a brief high-temperature anneal immediately afterward repairs the crystal and locks the dopants into place.

Coat, expose, carve, inject: repeat this cycle a few dozen times and the transistors are done; stack the copper interconnect on top and the circuits on the wafer are complete. But between being able to build it and making money on it lies the mathematics of yield.

The Mathematics of Yield: Big Dies Lose Exponentially

However clean the cleanroom, microscopic particles and film defects scatter randomly across every wafer. Call the density of killer defects $D_0$ (defects per cm²) and the area of one chip $A$. If a single defect landing on a die kills it, then treating defects as Poisson-distributed gives the fraction of good dies — the yield:

$Y$ is the yield (fraction of good dies) and $e$ is the base of the natural logarithm. Here $A \cdot D_0$ is the average number of defects landing on one die, and $e^{-A \cdot D_0}$ is the probability that a die of that size catches none of them — which says that yield is simply the chance of drawing a losing ticket zero times across the whole area of the die. It also says that doubling the area does not halve the yield, it squares it ($e^{-2AD_0} = (e^{-AD_0})^2$). The reading is simple: as die area grows, yield falls off exponentially. In a fab running at $D_0 = 0.1$/cm², a small 1cm² chip yields $e^{-0.1} \approx 90\%$. A giant die filling the single-exposure limit (the reticle limit, about 26×33mm) yields $e^{-0.86} \approx 42\%$. The same production line, but the choice of area alone sets the order of magnitude of your scrap rate. Half the reason cutting-edge AI accelerators are expensive is this equation.

The exponential bites a second time through the process itself. Suppose each of the hundreds of steps damages the wafer with some tiny probability. Even at 99.9% success per step, surviving 600 steps means $0.999^{600} \approx 55\%$. Losses invisible at any single step compound multiplicatively into nearly half the wafer.

The industry fights this math with three weapons. First, redundancy: memories are built with spare rows and columns, and failing cells are remapped to the spares. Second, binning: a GPU with a few defective compute units has them disabled and ships as a lower-tier product. Third, chiplets: split one huge die into several small ones to shrink the $A$ in equation (2), recover the yield, then bond them back together inside the package at high speed. The recent wave of chiplet-based processors isn't a design fashion — it's a defense against an exponential.

Check It in Code: Cost per Good Die

Let's translate equation (2) directly into money.

import numpy as np

def cost_per_good_die(area_cm2, d0, wafer_cost):
    wafer_area = np.pi * 15**2          # 300mm wafer ≈ 707 cm²
    dies = wafer_area / area_cm2        # ignoring edge losses
    y = np.exp(-area_cm2 * d0)          # Poisson yield model
    return wafer_cost / (dies * y)

for a in [1.0, 2.0, 4.0, 8.0]:
    print(a, round(cost_per_good_die(a, d0=0.1, wafer_cost=10000), 1))

Run it and you'll see that doubling the area more than doubles the cost per good die: you get half as many candidates per wafer, and a smaller fraction of them survive. This "compound interest on area" is why die size is on the agenda of every chip design meeting.

How This Is Used on the Job

Where the ideas in this article show up in real work:

• Lithography engineers sweep exposure dose and focus across a grid of conditions to establish the process window, then track linewidth with a CD-SEM (a measurement electron microscope) and overlay with dedicated metrology tools every day. What they are tuning is precisely the contents of $k_1$ in equation (1).
• Yield engineers read the "pattern" of a wafer map — a plot of good and bad dies by position — like a fingerprint. A ring of failures at the edge points to deposition or temperature non-uniformity; a straight scratch points to wafer handling; a uniform random scatter means $D_0$ itself has degraded. Their daily tools are $D_0$ trend charts and SPC (statistical process control) control charts.
• Designers are not exempt. Physical-design DRC (design rule checking) now embeds multi-patterning decomposition constraints, and every 10% of die area feeds back into product cost through equation (2).
• The trap is delayed feedback. A slight drift in one tool today surfaces as a yield drop at test weeks or months later. "Fix it when you notice" would condemn every wafer already in the line, which is why fabs rely on statistical monitoring to catch drift early. Separately, latent defects that slip past test would fail in the field, so parts are stressed under burn-in to weed out weak units first.
• A classic interview question: "If you double the die area, what happens to cost per good die?" The skeleton of the answer: 2× from getting half as many dies, multiplied by a further yield penalty — so "worse than 2×" — and you're expected to derive it from equation (2).

Summary

• A chip is not carved; it is printed in layers — coat, expose, carve, inject, repeated hundreds of times
• The resolution limit is $k_1 \lambda / NA$; immersion and multi-patterning squeeze it, EUV brute-forces the wavelength down 14×
• Yield is an exponential in both die area and step count; chiplets and binning are counterattacks on that math
• Cost per good die = wafer cost over (dies × yield), and area compounds against you

For the power constraints that can cook a finished chip, see The physics of power; for how compute and data movement compete on the finished chip, see The memory wall; and for how a GPU actually runs work on the silicon this process delivers, see The GPU execution model. Manufacturing, devices, and architecture are one continuous story.