Dark Silicon — You Can Place the Transistors, You Just Can't Light Them All

The number of transistors you can put on a chip keeps rising, but the fraction you can switch on at the same time keeps falling. That gap is dark silicon. We derive it from one line about power density, check the numbers against the 2011 ISCA paper that made the term quantitative (21% of a fixed-size chip off at 22 nm, more than 50% at 8 nm), and follow the argument to why specialised circuits won.

Half the outlets, none of the amps

Imagine an apartment with twenty power outlets and a breaker rated for 1500 W total. You can plug in a hairdryer, a microwave and a space heater, but not run them together. The number of outlets is one thing; how much you may draw at once is decided separately.

That is a modern chip. The transistor count keeps climbing, but switching all of them at once would cook the die. So designers plan around regions that stay off. Silicon that is fabricated but permanently dark is called dark silicon.

The definition in one sentence: the condition where heat limits keep a chip from running all of its transistors at once.

Two exponentials, only one of which kept going

The whole story is two curves.

• Transistors you can place kept doubling. That is what Moore's Law described.
• Heat you can remove barely moved. It is set by the package, the heat sink and the air around them, none of which improve when you shrink a feature.

For a while both scaled together, and the thing holding them together was Dennard scaling. The 1974 paper by Dennard and colleagues showed that if you shrink physical dimensions and the supply voltage by the same factor, the power per unit area — the power density — stays the same. If heat per area is constant, then more transistors do not mean more of a thermal problem. Shrinking was close to a free lunch: faster, and no hotter.

Around 2005 that relationship broke, because voltage stopped coming down.

Why voltage stalled — the ~60 mV/decade floor

The power a CMOS circuit pays to switch follows the dynamic power equation

$$P_{\text{dyn}} = \alpha C V^2 f$$

In words, the power a circuit pays to switch is the activity factor times the capacitance times the voltage squared times the frequency. Of these, only the voltage enters squared, so lowering it is the strongest lever available.

where $\alpha$ is the activity factor, $C$ the capacitance, $V$ the supply voltage and $f$ the frequency. Only $V$ enters squared, which is why lowering voltage is the strongest lever available — and why Dennard scaling worked at all.

But lowering the supply voltage means lowering the transistor's threshold voltage too, and there the physics pushes back. To turn a MOSFET further off, the voltage swing needed to cut the current by one decade has a lower bound. At room temperature it is

$$\frac{kT}{q}\ln 10 \;=\; \frac{1.380649\times10^{-23}\times298.15}{1.602\times10^{-19}}\times 2.3026 \;\approx\; 59.2\ \text{mV}$$

In words, the voltage swing needed to cut a transistor's off-current by one decade cannot go below a floor set by temperature itself, about 59.2 mV at 25 °C. This roughly 60 mV/decade limit comes from heat, not from how the circuit is built, and it is why the threshold voltage, and with it the supply voltage, could not keep dropping.

(evaluated at 25 °C; about 59.6 mV at 27 °C). The figure usually quoted as 60 mV/decade is not a limitation of how we build circuits — it comes out of temperature itself.

Push the threshold too low and the current leaking through a transistor that is supposed to be off grows exponentially. Circuits that are doing nothing start drawing power, so there is a practical floor. Supply voltages stalled near 1 V in the mid-2000s, and power density began to rise.

What ended was Dennard scaling, not Moore's Law. Conflating the two derails the argument. Transistors kept arriving. What stopped was our ability to pay for them.

The primary numbers — a 2011 projection: 21% at 22 nm, over 50% at 8 nm

The paper that turned "dark silicon" into a quantitative forecast is Esmaeilzadeh et al., presented at ISCA in 2011. They built Pareto-optimal area/performance and power/performance frontiers from measurements of over 150 processors, combined them with device scaling projections, and estimated the performance ceiling five technology generations out. From the abstract:

Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9× average speedup is possible across commonly used parallel workloads, leaving a nearly 24-fold gap from a target of doubled performance per generation.

So: on a fixed-size chip, 21% powered off at 22 nm and more than 50% at 8 nm; an average speedup of 7.9× by 2024, about 24× short of a doubling per generation.

This needs care. These are projections from a 2011 model, not measurements taken afterwards. The paper itself brackets the result with two device-scaling assumptions (ITRS projections and a more conservative set). Quote them as "the 2011 projection", not as today's numbers.

The direction, though, held. Designing around "we cannot light it all" became the mainstream position.

Three ways out when the budget is short

If you cannot run everything, you pick one of these.

1. Leave it off. Accept the dark area and power-gate what is idle.
2. Slow it down instead. Vary voltage and frequency with the workload — DVFS. Everything runs; nothing runs flat out.
3. Replace the circuit with one that does more work per watt. This is the interesting one.

The third option is why dark silicon is described as the reason dedicated circuits win. A general-purpose CPU carries a lot of machinery so it can execute whatever instruction shows up. A block that does nothing but matrix multiplication switches far fewer transistors per useful operation. The moment power — not area — is the binding constraint, spending area on efficient special-purpose blocks beats spending it on generality. The area was going spare anyway.

GPUs carrying AI workloads, inference performance being quoted per watt rather than per second, and low precision (BF16, FP8, INT8) becoming normal all fall out of this one constraint. Low precision helps for a concrete reason: fewer bits means fewer switching nodes, which shrinks $C$ in the dynamic power equation.

Three things it is not

① It is not silicon disabled because of defects. Switching off part of a die to route around a manufacturing fault is redundancy and repair — a yield question. Dark silicon is about circuits that came out fine and are held off for power reasons. Different cause entirely.

② It is not wasted transistors. Dark area gets filled with special-purpose blocks: video encode, crypto, matrix multiply, signal processing. You lay down a circuit per job and light only the one you need right now. Read it as trading area for efficiency, not as waste.

③ It is not the same thing as clocks not getting faster. Both follow from the end of Dennard scaling, but the clock wall is "we cannot run one circuit faster" while dark silicon is "we cannot run many circuits at once". The answer to the first was multicore; the answer to the second was specialisation.

Check it yourself

Dark silicon is a concept, but you can get a feel for the arithmetic.

# Area doubled; the power budget did not. What fraction can you light?
def lit_fraction(area_ratio, power_budget_ratio=1.0, perf_per_watt_gain=1.0):
    """area_ratio: transistors you can place, relative to the last generation
       power_budget_ratio: heat you can remove, relative (usually 1.0 = flat)
       perf_per_watt_gain: how much less power the same work now takes"""
    return min(1.0, power_budget_ratio * perf_per_watt_gain / area_ratio)

for gen, area in enumerate([1, 2, 4, 8], start=0):
    # Even with efficiency improving 1.3x per generation, 2x area outruns it
    print(gen, area, round(lit_fraction(area, 1.0, 1.3 ** gen), 3))

The shape that comes out is a fraction that falls every generation. Make the efficiency gain outpace the area growth and the fraction recovers — which tells you which side of the inequality a design is trying to move. The values are illustrative, not measurements from real parts.

How this shows up in practice

• Read "transistors are cheap, power is not" into the roadmap. Accelerators and new special-purpose instructions keep arriving because area is available and power is not. Conversely, optimisations that only save area are worth relatively less than they were.
• Divide performance by watts. The same operation count at different power means a different amount you can run concurrently. TOPS/W before TOPS is a consequence of this constraint, not a fashion.
• Do not expect shrinking to make things faster by itself. Dennard scaling is the part that ended, so a smaller node buys density; performance per watt has to be earned some other way.

Summary

• Dark silicon is the condition where heat limits keep a chip from running all of its transistors at once.
• The cause: transistor count grows exponentially while removable heat is roughly flat. Dennard scaling, which used to reconcile the two, broke around 2005 when supply voltage stopped falling.
• Underneath the voltage stall is a thermal floor of about 60 mV/decade (≈59.2 mV at 25 °C).
• The 2011 ISCA projection: 21% of a fixed-size chip off at 22 nm, over 50% at 8 nm, and only 7.9× average speedup through 2024.
• "You cannot light it all" is not a failure; it is the premise. It is the reason special-purpose circuits and low precision win.

For the derivation of the power equation and how to convert watts into degrees with thermal resistance, continue to The Physics of Power — Why Lowering Voltage Works So Well. For deciding the budget with actual numbers, see Reading Chip Design Through the Power Budget. For what ended and what continued in scaling, see Moore's Law in Practice, and for the specialised side, Accelerator Design.

Sources

• R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, A. R. LeBlanc, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," IEEE Journal of Solid-State Circuits, vol. 9, October 1974. — the original statement that power density stays constant under scaling.
• H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, "Dark Silicon and the End of Multicore Scaling," Proceedings of the 38th International Symposium on Computer Architecture (ISCA '11), June 2011. — the 21% / over 50% / 7.9× / ~24-fold figures quoted above come from this abstract. They are 2011 projections.
• The ~60 mV/decade figure is $(kT/q)\ln 10$ evaluated at room temperature; the arithmetic is shown inline.