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#semiconductor

13 articles

01 ·Supply Chain·FREE·8 min read Mapping the Semiconductor Supply Chain — From Sand to Chip, Who Holds What One pass through the whole chain that makes a chip — design (EDA/IP), equipment, materials, foundry, OSAT — and why nearly every stage collapses to a handful of firms, read through two formulas: chain availability and HHI. 02 ·Supply Chain·★ MEMBER·13 min read Upstream of Semiconductors — Wafers, Photoresist, and Specialty Gases How sand becomes silicon that is 99.999999999% pure, gets pulled out of a melt as one giant single crystal, and is coated with a film that dissolves where light hits it. From segregation in the Czochralski process to acid blur in chemically amplified resist — and why a handful of Japanese firms still own this layer. 03 ·Supply Chain·★ MEMBER·9 min read Inside the Equipment Makers — What ASML, AMAT, TEL and Lam Actually Build Chip manufacturing is four actions repeated hundreds of times — deposit, print, etch, clean — and each action has its own machine and its own specialist vendor. After mapping steps to suppliers, two pieces of arithmetic explain why the tool business collapses into a handful of firms, and why ASML's EUV monopoly is really a bundle of irreplaceable component makers. 04 ·Supply Chain·★ MEMBER·10 min read EDA Tools from Scratch — Chips Are Written in Software Nobody hand-places the tens of billions of transistors on a leading-edge chip. Designers write text (RTL), and software compiles it into physical geometry through synthesis, place-and-route, and verification. Here is that pipeline from zero, plus why Synopsys and Cadence became impossible to route around. 05 ·Supply Chain·★ MEMBER·9 min read The Geopolitics of Chips — Export Controls and Supply Chain Rewiring, Explained Technically Why chokepoints form exactly where they do, from three conditions: physics, fixed cost, and tacit knowledge. Covers the technical reason controls are written as numeric thresholds, the common-cause formula that kills dual sourcing, and the learning curve that sets how fast a substitute can arrive. 06 ·Device Physics·★ MEMBER·12 min read The Physics of NAND Flash — Remembering by Trapping Electrons Why does a memory stick keep your photos with the power off? Starting from one idea — trap electrons on an island of insulator and shift a threshold voltage — this article builds up tunnelling writes, multi-level cells, 3D stacking and wear-out, and ends where you can read an SSD datasheet and a SMART log for yourself. 07 ·Fabrication & Packaging·★ MEMBER·11 min read Yield and Design — DFM, the Art of Giving Something Up A circuit can be correct in simulation and still fail to make money in volume. Defect density models and the clustering factor, design rules that restrict what shapes you may draw, redundancy that assumes breakage, and binning that turns one die into several products — the engineering of trading performance for yield, from first principles. 08 ·Device Physics·★ MEMBER·9 min read From FinFET to GAA — Why the Transistor Had to Go Vertical Why did a flat transistor grow a fin, and then become a stack of thin slabs? With three tools — short-channel effects, DIBL, and the natural length — this piece shows that FinFET and GAA nanosheets were not a matter of taste but a corner physics painted the industry into. No prior knowledge assumed. 09 ·Device Physics·FREE·11 min read Band Theory from the Ground Up — Why It Had to Be Silicon What actually separates a conductor from an insulator? Starting from why atomic energy levels smear into bands, this piece builds up bandgaps, Fermi statistics and doping with no prior physics assumed — and lands on the real answer to 'why is every chip made of silicon', which turns out to be about the oxide, not the element. 10 ·Scaling & Power·FREE·10 min read What Moore's Law Actually Says — What Ended, and What Is Still Going "Double every two years" was never a law of physics — it was a timetable the industry agreed to keep. Dennard scaling is what ended; cost is what slowed; density and going vertical are what continue. A ground-up tour through log axes, the flat-to-FinFET-to-GAA story, and the arithmetic of cost per transistor. 11 ·Fabrication & Packaging·★ MEMBER·10 min read EUV Lithography — The Madness of Making 13.5nm Light Light at 13.5nm is absorbed by air and by every lens material there is. So why did the semiconductor industry build an entire industry around it? Tin plasma sources, optics with no lenses at all, and the cost arithmetic against multi-patterning — explained from zero. 12 ·Fabrication & Packaging·★ MEMBER·9 min read How Chips Are Made — From Wafer to Yield Every GPU and phone processor starts as sand and passes through hundreds of printing steps. From the basic moves — lithography, etching, ion implantation — to the brute force of EUV and the yield math that makes big dies exponentially expensive, explained from zero. 13 ·Device Physics·FREE·9 min read MOSFETs from the Ground Up — A Sluice Gate Opened by Voltage, and the Reality of Leakage The switch that fills every CPU and GPU, assuming no prior knowledge. From the sluice-gate analogy to threshold voltage, then the subthreshold leakage equation and why shrinking a transistor makes it leak more — the root of the power problem in one article.