#accelerator

4 articles

01 ·Scaling & Power·FREE·8 min read Dark Silicon — You Can Place the Transistors, You Just Can't Light Them All The number of transistors you can put on a chip keeps rising, but the fraction you can switch on at the same time keeps falling. That gap is dark silicon. We derive it from one line about power density, check the numbers against the 2011 ISCA paper that made the term quantitative (21% of a fixed-size chip off at 22 nm, more than 50% at 8 nm), and follow the argument to why specialised circuits won. 02 ·Computer Architecture·★ MEMBER·PAPER·10 min read Systolic Arrays — Building the Heart of the TPU From Scratch Piling on multipliers doesn't make a chip faster, because moving data costs more than the arithmetic does. This piece takes the grid at the center of the TPU — the systolic array — and shows exactly how it maps the triple loop of matrix multiplication onto rows, columns and clock ticks, from a 2×2 hand trace to a cycle-accurate simulator to the batch-size and shape rules you'll actually tune. 03 ·Accelerators·★ MEMBER·10 min read The Inference Chip Wars — Inside the Design Philosophies of Groq, Cerebras, and the LPU Inference-only chips exist because decoding is limited by reading, not by arithmetic. From zero background: the two answers — put everything in SRAM (Groq/LPU) and make the chip a whole wafer (Cerebras) — the software counterattack, and the arithmetic you need to read the market without swallowing vendor benchmarks whole. 04 ·Accelerators·★ MEMBER·PAPER·8 min read How AI Accelerators Are Designed — What Actually Separates GPUs, NPUs, and TPUs GPUs, TPUs, and NPUs are three different answers to one question: how much generality do you trade away for matrix multiplication? A from-scratch tour of systolic arrays, dataflow design, and the co-evolution of hardware and quantization.