#accelerator
3 articles
01
·Computer Architecture·★ MEMBER·PAPER·10 min read
Systolic Arrays — Building the Heart of the TPU From Scratch
Piling on multipliers doesn't make a chip faster, because moving data costs more than the arithmetic does. This piece takes the grid at the center of the TPU — the systolic array — and shows exactly how it maps the triple loop of matrix multiplication onto rows, columns and clock ticks, from a 2×2 hand trace to a cycle-accurate simulator to the batch-size and shape rules you'll actually tune.
02
·Accelerators·★ MEMBER·9 min read
The Inference Chip Wars — Inside the Design Philosophies of Groq, Cerebras, and the LPU
Inference-only chips exist because decoding is limited by reading, not by arithmetic. From zero background: the two answers — put everything in SRAM (Groq/LPU) and make the chip a whole wafer (Cerebras) — the software counterattack, and the arithmetic you need to read the market without swallowing vendor benchmarks whole.
03
·Accelerators·★ MEMBER·PAPER·8 min read
How AI Accelerators Are Designed — What Actually Separates GPUs, NPUs, and TPUs
GPUs, TPUs, and NPUs are three different answers to one question: how much generality do you trade away for matrix multiplication? A from-scratch tour of systolic arrays, dataflow design, and the co-evolution of hardware and quantization.