Students Professional
JA EN

#verification

3 articles

01 ·Supply Chain·★ MEMBER·10 min read EDA Tools from Scratch — Chips Are Written in Software Nobody hand-places the tens of billions of transistors on a leading-edge chip. Designers write text (RTL), and software compiles it into physical geometry through synthesis, place-and-route, and verification. Here is that pipeline from zero, plus why Synopsys and Cadence became impossible to route around. 02 ·Paper Deep-Dives·★ MEMBER·PAPER·13 min read Paper Walkthrough: Turning Game Development into a Verifiable Trajectory Data Engine — RLHEV and AWoMo A paper arguing that what world models lack is not data or compute but cheap grading. We work through RLHEV — post-training on game-engine checks fused with developer accept/reject decisions — from first principles to equations, interactive figures, and the reported numbers. 03 ·Agents·★ MEMBER·PAPER·13 min read Paper Explainer: SemaPLC — The Agent That Isn't Allowed to Say "Done" Most work on LLM-generated factory control code stops at showing that the code can run. SemaPLC forbids the agent from declaring completion until logged external checks confirm it, lifting live-runtime behavior from a baseline ceiling of 31.4 to 52.2.