Accelerators
Number formats, accelerator design styles, edge deployment
01
·Accelerators·★ MEMBER·PAPER·8 min read
How AI Accelerators Are Designed — What Actually Separates GPUs, NPUs, and TPUs
GPUs, TPUs, and NPUs are three different answers to one question: how much generality do you trade away for matrix multiplication? A from-scratch tour of systolic arrays, dataflow design, and the co-evolution of hardware and quantization.
02
·Accelerators·FREE·9 min read
How Numbers Are Represented — From FP32 to FP8 and INT4
Open up the sign, exponent and mantissa fields and one rule falls out: the exponent buys range, the mantissa buys precision. From there — why bfloat16 was invented, why FP8 ships in two flavours, and what integer quantization actually destroys. Ends with which format to pick for training versus inference, and how to notice degradation before your users do.
03
·Accelerators·★ MEMBER·9 min read
The Inference Chip Wars — Inside the Design Philosophies of Groq, Cerebras, and the LPU
Inference-only chips exist because decoding is limited by reading, not by arithmetic. From zero background: the two answers — put everything in SRAM (Groq/LPU) and make the chip a whole wafer (Cerebras) — the software counterattack, and the arithmetic you need to read the market without swallowing vendor benchmarks whole.